This project was done as a part of the Microprocessors course at IIT Bombay. The microprocessor design was done for both multi-cylce and pipleined architecture. The theory required for the project was taught alongisde during 5th Semester in my undergraduate course by Prof Virendra Singh, IIT Bombay.
Documentation and Code
Multicycled IITB-RISC :- https://github.com/thechargedneutron/IITB-RISC
Pipelined IITB-RISC :- https://github.com/thechargedneutron/Pipelined-IITB-RISC